1. Field of the Invention
The invention generally relates to data retention circuits that retain data during a “low power mode” in which power is removed from certain main circuitry. More particularly, the invention relates to ultra low-power data retention circuits in which it is desired to quickly save data from a main latch to a slave latch, and to quickly replenish the main data latch with retained data, all while minimally loading main data latch data output lines during normal operation.
2. Related Art
In low-power chips, much of the circuitry is shut down when not in use (in a “low power mode”) so as to conserve power. However, some parts of the circuit remain powered during low power mode, to retain data. This retained data is used again when the chip emerges from low power mode.
Various back-up data latch arrangements are known in the art. However, in some known arrangements, there is a need to explicitly disable the main latch while awaiting or during stable power restoration. In some conventional arrangements, additional gates or signals are required in order to disable the main data path until power is stably restored. Also, some known latch arrangements require additional isolation or buffer circuitry, or have a circuit topology, that effectively add to the time required to pass data through the latch, undesirably slowing data throughput. For example, in certain conventional retention latches, the back-up latch's lines are connected the data output nodes of the main latch, adding loading to the main data path; undesirably, more time is needed for the main latch to correctly resolve before the main data path can safely be enabled. Also, certain known arrangements require power to the main latch to be kept off until data is restored to the normal output path, slowing the circuit's return to normal operation. Furthermore, some conventional latch arrangements simply consume undesirably large amounts of power.
Accordingly, there is a need in the art for a fast, ultra low-power arrangement that avoids the need to provide explicit disablement of a main latch and that does not require additional gates or signals to achieve disablement of the main data path.